This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a low-voltage, low-power DC generator system for a semiconductor chip.
Semiconductor memory units embedded within an integrated circuit (IC) system are arranged in arrays of cells, where each cell stores one bit of information (1 or 0). Generally, in order to maintain the integrity of the data stored within an embedded semiconductor memory unit, such as an embedded dynamic random access memory unit (eDRAM), each cell of the memory unit requires periodic refreshing, since a small charge stored in each cell of the memory unit tends to leak off due to several factors, such as an increase in the temperature of the chip. Accordingly, circuitry is required to manage or control such semiconductor memory units for refreshing the cells, as well as read or write data from or to the memory array. Hence, these circuits consume power causing a reduction in the lifetime of the battery when these circuits are utilized in hand-held, battery-operated devices.
The refresh read or write circuitry generally includes at least one DC voltage generator system having several charge pump circuits for providing different voltage and current supplies to cells and other circuits of the memory unit. For example, three typical charge pump circuits for the eDRAM are the substrate bias circuit or Vbb charge pump circuit, the negative wordline low bias circuit or Vwl charge pump circuit, and the boost wordline high voltage circuit or Vpp charge pump circuit. A respective constant-speed ring oscillator provided in proximity or within the memory unit is generally used to run each of these charge pump circuits. A typical frequency range for the oscillator is from 5 MHZ to 50 MHZ depending on the voltage or current required to be produced by the particular charge pump circuit.
For example, for the Vbb charge pump circuit, the required capacity is low, and therefore, a 5 MHZ oscillator is sufficient. On the other hand, for the Vwl charge pump circuit, which is designed to sink large amount of current during an active mode, a 40 MHZ oscillator is required. However, during a standby or sleep mode, when there is no access to the word-lines, a lower capacity standby charge circuit supported by a lower-speed oscillator is needed for the Vwl charge pump circuit to save power. Therefore, two oscillator circuits with different capacities are needed for the Vwl charge pump circuit, i.e., one for each mode.
Further, when the supply or operating voltage, i.e, Vdd, of the memory unit starts to drop, e.g., when power output from a battery decreases, the charge produced by the charge pump circuits is affected. For example, if the peak current provided by the Vpp charge pump circuit is 4 mA when Vdd is 1.8V, when the Vdd drops from 1.8V to 1.5V and lower, the peak current provided by the Vpp charge pump circuit is much less than 4 mA. This results in performance degradation of the memory unit which could lead to data corruption or loss, since the cells of the memory unit would not be adequately restored or refreshed.
Therefore, in order to efficiently operate the charge pump circuits, the voltage provided to the charge pump circuits must be kept at a high level, i.e., prevented from dropping to a lower level. This condition necessitates that the period of time between activation of the DC voltage generator system be decreased to prevent the voltage provided to the charge pump circuits from dropping. This results in a great amount of power to be consumed by the DC voltage generator system, especially since the DC voltage generator system is operated at a high voltage. The high power consumption of the DC voltage generator system can significantly reduce battery lifetime.
Additionally, the high consumption of power by the DC voltage generator system causes the chip temperature to increase, thereby further necessitating a further decrease in the period of time between activation of the DC voltage generator system and refresh cycles of the charge pump circuits. This further causes a reduction in the battery lifetime.
As a consequence of the DC voltage generator system consuming a relatively large amount of power, memory units are generally designed with a few or no additional circuits for adding additional features to the memory unit, such as band-gap reference circuit for providing a band-gap reference voltage, and a temperature sensor circuit for approximating the chip temperature. Further, when these additional circuits are added to the memory unit, they not only consume a great amount of power, but, as a consequence of consuming a great amount of power, they further facilitate the increase in the chip temperature. As indicated above, an increase in the chip temperature causes a decrease in the period of time between activation of the DC voltage generator system and refresh cycles of the charge pump circuits, thereby draining the battery at a more rapid rate.
Additionally, the DC voltage generator system is designed to be operated at a high supply voltage because the threshold voltage of the charge pump circuits cannot be scaled in a same rate as the supply voltage. That is, if the supply voltage is at or near one-volt scaled from a high voltage level, the threshold voltage of the charge pump circuits cannot be scaled at the same rate as the supply voltage to reach the appropriate threshold voltage level. If the threshold voltage of the charge pump circuits is scaled at the same rate as the supply voltage, the DC current at standby will be out of control. As a result, if the supply voltage is dropped to at or near one-volt, the operating efficiency of the charge pump circuits is greatly degraded, because the threshold voltage of the charge pump circuits cannot be scaled at the same rate as the supply voltage.
The prior art, in the field of low-power logic applications, teaches adding at least one intermediate device having a variable threshold voltage between two logic circuits which require their operating voltages to be scaled. However, the prior art does not teach scaling the supply voltage of a DC voltage generator system with the threshold voltage of at least one charge pump circuit therein, and especially, when the supply voltage of the DC voltage generator system is at or near one-volt.
The prior art further teaches using a cascaded design to reach the appropriate voltage output level of a charge pump circuit. For example, to generate a 2.5 output voltage level, a DC voltage generator system can be implemented with a two-stage cascaded pump circuit; a pump circuit is connected in the first stage to generate an intermediate voltage supply, which in turn feeds another pump circuit in the second stage to generate the 2.5 output voltage level. However, such a cascaded design is prone to the ripple effect, i.e., the voltage output drops below a low limit level and rises above a high limit level due to delays in signaling the pump circuit to power on or off. Further, the prior art does not teach the use of a cascaded design when the supply voltage of the DC voltage generator system is at or near one-volt.
Accordingly, a need exists for a DC voltage generator system capable of operating at low-power, and especially, when the supply voltage is at or near one-volt, e.g., in the range of 0.5 to 1.7 volts, while maintaining operating efficiency of the charge pump circuits, in order to reduce power consumption, maximize system performance, minimize the surface area required in implementing the memory unit, and maintain the integrity of the data stored within the memory unit.
A need further exists for a DC voltage generator system capable of operating at low-power, and especially, when the supply voltage is at or near one-volt, and includes at least one intermediate device between two circuits having different operating or threshold voltages.
Further, a need exists for a DC voltage generator system capable of operating at low-power, and especially, when the supply voltage is at or near one-volt, and includes a cascaded design which is not substantially prone to the ripple effect.
An objective of the present invention is to provide a DC voltage generator system for a semiconductor chip, such as a memory, microprocessor, or logic, where the DC voltage generator can be operated at low-voltage and low-power.
Another objective of the present invention is to provide a DC voltage generator system capable of operating at low-power, and especially, when the supply voltage is at or near one-volt, and includes at least one intermediate device between two circuits having different threshold voltages.
Further, another objective of the present invention is to provide a DC voltage generator system capable of operating at low-power, and especially, when the supply voltage is at or near one-volt, and includes a cascaded design which is not substantially prone to the ripple effect.
Further still, another objective of the present invention is to provide a DC voltage generator system for a memory unit, such as an eDRAM memory unit or CPU chip, for activating charge pump circuits therein to refresh data cells of the memory unit, while maintaining operating efficiency of the charge pump circuits, maximizing system performance, minimizing the surface area required in implementing the memory unit, and maintaining the integrity of the data stored within the memory unit.
Still, another objective of the present invention is to implement the low-power DC voltage generator system within a battery-operated device having at least one memory unit. The low-power DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.
Accordingly, the present invention provides a low-power DC voltage generator system having two negative voltage pump circuits for generating voltages for operating the Vwl and Vbb charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating the Vpp charge pump circuit or boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt.
The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.